Test Set Compaction Considering Test Application Time in Full Scan Circuits

Author

Sapan Basaula, Southern Illinois University CarbondaleFollow

Date of Award

8-1-2022

Degree Name

Master of Science

Department

Electrical and Computer Engineering

First Advisor

Tragoudas, Spyros

Abstract

With the increasing number of transistors in the circuit, the time it requires to label the circuit as defect-free also increases. Test application time plays a major role in increasing yield in manufacturing. This thesis presents an approach to generate a test set to detect manufacturing faults considering the test application time. The test set is constructed using an initial compact test set and by utilizing the output signature of the test vectors and increasing the overlap with a succeeding test vector. The novelty of the approach is the consideration of the essential faults for the test generation of the optimal test vector and the distribution of those faults among other test vectors if such a test vector is not possible. The test generation of the optimal test vector is done using structural and SAT-based approach. The generated test set retains the fault coverage without any additional hardware overhead. The experimental results on the ISCAS89 benchmark circuit show significant reductions in the test application time.