Reduction of Cache Related Preemption Delay using DVS in Real Time Systems

Author

Aravind Chandrashekar, Southern Illinois University CarbondaleFollow

Date of Award

5-1-2011

Degree Name

Master of Science

Department

Electrical and Computer Engineering

First Advisor

Ramaprasad, Harini

Abstract

Aravind Chandrashekar, for the Master of Science degree in Electrical and Computer, presented on 02/09/2011, at Southern Illinois University Carbondale. TITLE: Reduction of Cache Related Preemption Delay using DVS in Real Time Systems MAJOR PROFESSOR: Dr. Harini Ramaprasad Embedded/real-time systems are ubiquitous in today's world. Providing temporal guarantees is paramount in such systems. In several multi-tasking real-time systems, tasks are assigned varying priorities and scheduled in accordance with a preemptive scheduling policy. When a task is preempted, a significant number of memory blocks belonging to the particular task are displaced from the cache memory between the time that the task is preempted and the time that the task resumes execution. Upon resumption, a corresponding amount of time is spent in reloading the cache with previously replaced memory blocks, thereby incurring what is known as cache-related preemption delay (CRPD). CRPD of a task due to a given preemption depends on the position in the program where the preempted task is executing at the time of preemption. As such, CRPD at different preemption points may be significantly different. In this thesis, we exploit this difference in CRPD and use dynamic voltage/frequency scaling (DVFS) to control the execution speed of a task such that it gets preempted in regions where the CRPD is low, as far as is possible without jeopardizing system schedulability. Simulation results demonstrate that our algorithm reduces number of cache reloads due to preemption to a reasonable extent, thereby reducing the repeated usage of off-chip memory bandwidth.