IMPLEMENTATION OF A 10-BIT A-SAR ADC CIRCUIT BASED ON VOLTAGE TO TIME CONVERSION

Author

Suresh Koyada, Southern Illinois University CarbondaleFollow

Date of Award

5-1-2016

Degree Name

Master of Science

Department

Electrical and Computer Engineering

First Advisor

wang, haibo

Abstract

SURESH KOYADA, for the Master of Science degree in Electrical and Computer Engineering, presented on November 17th 2015, at Southern Illinois University Carbondale. TITLE: IMPLEMENTATION OF A 10-BIT A-SAR ADC CIRCUIT BASED ON VOLTAGE TO TIME CONVERSION MAJOR PROFESSOR: Dr. Haibo Wang Comparators are widely used in analog to digital converters. However, the scaling of CMOS technologies makes the design of low power voltage comparators difficult. In order to overcome this problem time-based comparators are introduced which are suitable for nanometer CMOS technology and low supply voltages. This thesis presents the transistor level implementation of a 10-bit time-based accelerated SAR ADC with a supply voltage of 0.5 V. The design increases the conversion speed compared to conventional SAR ADC by updating the upper bound and lower bound of the search space more aggressively. Various design issues, including optimal switch design, glitch minimization at the charge scaling capacitor array output are discussed. This design achieves a SNDR of 58.78dB at a sampling rate of 90.9kS/s and ENOB (effective number of bits) of 9.47 bits with a power consumption of 280nW.