A 200-833 MHz Delay Locked Loop for DDR Applications

Author

Brett Patrick Delaney, Southern Illinois University CarbondaleFollow

Date of Award

5-1-2016

Degree Name

Master of Science

Department

Electrical and Computer Engineering

First Advisor

Haniotakis, Themistoklis

Abstract

As memory I/O bandwidth continues to increase beyond the current multi-gigabit rates for high performance computer systems, there remains a need for a stable and robust method of clock synchronization capable of transferring data reliability between main memory and a CPU memory controller. A Delay Locked Loop (DLL) is often utilized in such a system where synchronization and removal of clock skew are necessary. Synchronization in DLL’s is carried out by continually adjusting the phase of a clock signal by adding or removing delay based on feedback provided by a Phase Detector (PD). Once phase alignment occurs, the DLL is said to be in a “Locked” state. Delay can be produced with either a VCDL (Voltage Controlled Delay Line), or a DCDL (Digitally Controlled Delay Line). Each type of delay line has their own benefits and drawbacks, many of which will be discussed throughout this paper. This thesis provides an overview of previous DLL design research, and presents a functional 45nm CMOS, 200-833 MHz delay locked loop.