A SIMPLE FPGA - BASED ARCHITECTURE DESIGN OF RECONFIGURABLE NEURAL NETWORK

Author

Jaber Salem, Southern Illinois University CarbondaleFollow

Date of Award

5-1-2013

Degree Name

Master of Science

Department

Electrical and Computer Engineering

First Advisor

Botros, Nazeih

Abstract

In contrast with analog design, digital design and implementation of any logic circuit suffer much from the difficulty in terms of economy and implementation. Neural networks are artificial systems inspired by the brain's cognitive behavior, which can learn tasks with some degree of complexity, such as, optimization problems, text and speech recognition. Since the topology of neural networks is highly crucial to the performance, the reconfigurable ability of the neural network hardware is very essential. Reconfigurability factually means several different designs can be implemented on a single architecture. Therefore, this work proposes an efficient architecture to implement the reconfigurable back propagation and Hopfield neural networks. We specifically adopted the reconfigurable artificial neural networks approach to show how it is possible to build an efficient chip. Simple neural network models with an appropriate training were used to behave as traditional logic functions in the bit- level. In order to further reduce the hardware, memories-sharing method has been adopted. Also, a comparison between the proposed and traditional networks shows that the proposed network has significantly reduced the time delay and power consumption. Xilinx - ISE is used to synthesize our design. VHDL code is used to build the architecture. The architecture code is then downloaded to FPGAs (Field Programmable Gate Array) to implement the design. FPGAs are strong tools to implement ANNs as one can exploit concurrency and rapidly reconfigure to adapt the weights and topologies of an ANN. Also, XPower, as one of the best tools in Xilinx, was used to measure the total required power by our architecture. Finally, the results showed that the proposed reconfigurable architecture leads to a considerable decrease in the consumed power to almost 43% as well as the total time delay. Also, the architecture can easily be scalable as a future work and is able to cope with several network sizes with the same hardware.