Abstract
This paper proposes a novel approach to reducing the size of FPGA reconfiguration bits reams by fixing appropriate orders for LUT inputs. With such LUT input orders, memory locations that need to be altered during partial reconfiguration are relocated into common frames. We present a novel problem formulation that relates the number of frames (that need to be downloaded into FPGAs) to the number of minterms of a specially constructed logic function. A heuristic procedure is developed to solve the formulated problem in polynomial time. The proposed methodology is validated by experiments conducted on Xilinx Virtex FPGA platform. Considerable reduction on the size of reconfiguration bitstreams have been observed from our experimental results.
Comments
Published in Raghuraman, K.P., Wang, H., & Tragoudas, S. (2005). A novel approach to minimizing reconfiguration cost for LUT-based FPGAs. Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05), 673-676. doi: 10.1109/ICVD.2005.25 ©2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.