Abstract
A low power current sensing scheme for CMOS SRAM is presented in this paper. The proposed scheme includes a modified current conveyor as the column selector, and a new designed low power current sense amplifier to sense the small differential current signals in data lines. The output of the sense amplifier is fed to a clock control RS latch both for power reduction and longer output valid time. This current sensing scheme is clocked asynchronously and the timing control circuits are also discussed. Simulation results show that a sensing speed with 3ns less is achieved by this scheme and the sensing speed is insensitive to both bit line and data line capacitances.
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Comments
Published in Wang, H., & Liu, P.C. (1996). A low power current sensing scheme for CMOS SRAM. Records of the 1996 IEEE International Workshop on Memory Technology, Design and Testing, 37-45. ©1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.