A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

Authors

Xiaoqiang Li, Tianjin University of TechnologyFollow
Jingwei Zhang, RF microelectronics CorpFollow
Yuanzhi Zhang, Southern Illinois University CarbondaleFollow
Wenshen Wang, RF Microelectronis CorpFollow
Huimin Liu, Southern Illinois University CarbondaleFollow
Chao Lu, Southern Illinois University CarbondaleFollow

Comments

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License.

Recommended Citation

Li, Xiaoqiang, Zhang, Jingwei, Zhang, Yuanzhi, Wang, Wenshen, Liu, Huimin and Lu, Chao. "A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur." International Journal of Electronics and Communications 85 (Winter 2017): 23-31. doi:10.1016/j.aeue.2017.12.025.