Abstract
Modern resolver-to-digital converters (RDC) are typically implemented using DSP techniques to reduce hardware footprint and enhanced system accuracy. However, in such implementations, both resolver sensor and ADC channel unbalances introduce significant errors particularly in the speed output of the tracking loop. The frequency spectrum of the output error is variable depending on the resolver mechanical velocity. This paper presents the design of an auto-tuning output filter based on the interpolation of pre-computed filters for a DSP-based RDC with a type-II tracking loop. A fourth-order peak and a second-order high pass filter are designed and tested for an experimental RDC. The experimental results demonstrate significant reduction of the peak-to-peak error in the estimated speed.
Recommended Citation
Abou Qamar, Nezar, Hatziadoniu, Constantine J. and Wang, Haibo. "Speed Error Mitigation for a DSP-Based Resolver-to-Digital Converter Using Auto-Tuning Filters." 62, No. 2 (Feb 2015): 1134-1139. doi:10.1109/TIE.2014.2336622.
Comments
(c) 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works
The paper is published in the IEEE Transactions on Industrial Electronics, Vol 62-2, Feb 2015, pp 1134-9.