Built-In Schemes for Test Pattern Generation and Fault Location

Author

Snehal Udar, Southern Illinois University CarbondaleFollow

Date of Award

8-1-2011

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

First Advisor

Kagaris, Dimitri

Abstract

Snehal Udar, for the Doctor of Philosophy degree in Electrical and Computer Engineering, presented on May 4, of 2011, at Southern Illinois University Carbondale. TITLE: BUILT-IN SCHEMES FOR TEST PATTERN GENERATION AND FAULT LOCATION MAJOR PROFESSOR: Dr. D. Kagaris In this dissertation, we studied the areas of test pattern generation and fault location for detecting and diagnosing the faults in today's complex chips. In the first problem, a novel reseeding based test pattern generation scheme is analyzed by proposing a hardware efficient technique that uses irreducible polynomial-primitive element pair to generate distinct subsequences of test patterns. It is shown that for the given characteristic polynomial the hardware cost remains the same irrespective of the number of seeds required to generate the test sequence of given length. This scheme is targeted at generating pseudo-random test patterns that detect easy-to-detect faults. A counter based reseeding scheme is further analyzed that embeds a given set of fully specified test patterns in minimum number of clock cycles. Second problem investigates the effectiveness of inserting observation points on the circuit lines that along with primary output lines distinguish a given set of faults. Three hardware based approaches are proposed that aim at inserting minimum observation points, and are compared with each other for different diagnostic resolutions.