Online and Built-in self-testing techniques for Field Programmable Analog Array

Author

Amit Laknaur, Southern Illinois University CarbondaleFollow

Date of Award

12-1-2010

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

First Advisor

Wang, Haibo

Abstract

This research develops a built-in self-testing (BIST) and online testing techniques for switched capacitor (SC) based Field Programmable Analog Arrays (FPAAs). Particularly, a BIST technique for programmable capacitor arrays (PCAs), which are essential building blocks in the SC based FPAAs, is developed and its efficiency is analyzed. The proposed BIST technique results in very little hardware overhead and can be easily implemented on FPAAs. Techniques to model the impact of parametric faults on the performance of programmable capacitor arrays are also developed. Closed-form equations are derived for estimating ranges of parametric faults that can be detected by the proposed PCA testing circuits and methods to improve PCA testing efficiency are also discussed. Secondly, a comprehensive methodology is developed to perform online testing of SC based FPAA circuits. By taking advantage of the programmable resources, the proposed method can effectively test various sections of the FPAA circuits. Techniques to effectively partition FPAA circuits for online testing as well as methods to address circuit stability issues are presented. Factors that affect the testing accuracy of the proposed method are also studied. Error sources in the proposed testing circuit are investigated and methods to improve the accuracy of testing results are presented. Furthermore a novel programmable analog comparator is developed whose error threshold can be adaptively adjusted according to its input signal levels. It is ideal for analog online testing applications for enhanced testing accuracy due to the fact that its programmability allows the end user to adapt the error threshold to the testing needs. Analytical equations for guiding the design of proposed comparator circuitry are derived. The proposed comparator circuit has been designed and fabricated using a CMOS 0.18 micro-meter technology. Measurement results of the fabricated chip are presented.