ARCHITECTURE-AWARE MAPPING AND SCHEDULING OF MIXED-CRITICALITY APPLICATIONS ON MULTI-CORE PLATFORMS

Author

Aishwarya Vasu, Southern Illinois University CarbondaleFollow

Date of Award

5-1-2018

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

First Advisor

Kagaris, Dimitrios

Second Advisor

Ramaprasad, Harini

Abstract

The desire to have enhanced and increased feature sets in embedded applications has contributed to a significant increase in the computational demands of such systems over the years. To support such demand and yet maintain reasonable power/energy budgets, the industry has begun a shift to multi-core architectures even in the embedded systems domain. Embedded real-time applications such as Avionics and Automotive systems are no exception to this trend. Such systems have strict certification requirements of subsets of their functionality, which result in strict temporal constraints on those subsets, while other subsets may have less strict requirements. Migrating such {\em mixed criticality} systems from single-core to multi-core platforms is challenging because application/component isolation and freedom from interference among them must be guaranteed. Safe and efficient, architecture-aware mapping and scheduling of system components (e.g., partitions, tasks, etc. as relevant to a particular domain) on the multiple cores is at the center of any scheme to migrate such systems from single-core to multi-core platforms. In this dissertation, we propose, develop and evaluate a unified framework to automate the mapping and scheduling process with the consideration of several architectural and application level requirements/constraints (e.g., communication and cache conflicts among system components, constraints prohibiting the allocation of certain system components on the same core, etc.)