Date of Award
Master of Science
Electrical and Computer Engineering
Scan Chains in DFT has gained more prominence in recent years due to the increase in the complexity of the sequential circuits. As the test time increases along with the number of memory elements in the circuit, new and improved methods came in to prominence. Even though scan chain increases observability and controllability, a big portion of the time is wasted while shifting in and shifting out the test patterns through the scan chain. This thesis focus on reducing the number of clock cycles that are needed to test the circuit. The proposed Algorithm uses modified shift procedures based on 1) Finding hard to detect faults in the circuit. 2) Productive way to generate test patterns for the combinational blocks in between the flip flops. 3) Rearranging test patterns and changing the shift procedures to achieve fault coverage in reduced number of clock cycles. In this model, the selection process is based on calculating the fault value of a fault and total fault value of the vector which is used to find the hard faults and the order in which the vectors are applied. This method reduces the required number of shifts for detecting the faults and thereby reducing the testing time. This thesis concentrates on appropriate utilization of scan chains for testing the sequential circuits. In this context, the proposed method shows promising results in reduction of the number of shifts, thereby reducing the test time. The experimental results are based on the widely cited ISCAS 89 benchmark circuits.
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