Date of Award


Degree Name

Master of Science


Electrical and Computer Engineering

First Advisor

Haniotakis, Themistoklis


Significant characteristic of any VLSI design circuit is its power, reliability, operating frequency and implementation cost. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. This thesis describes the design and the optimization of high performance carry select adder. Previous researchers believed that existing CSA designs has reached theoretical speed bound. But, only a considerable portion of hardware resources of traditional adders are used in worst case scenario. Based on this observation our proposed design will improve on theoretical limit. The major scope of this proposed design is to increase the speed of carry generation between intermediate blocks of Carry select Adder (CSA) by introducing fast multiple clock Domino Manchester carry chain (MCC) that generates carry outputs. This design technique will have some advantages compared to pre-existing implementations in operating speed and power delay product. Simulation has been done using GPDK (Generic Process Design Kits) technology using cadence virtuoso. Thus the proposed technique provides advantages over pre-existing techniques in terms of operating speed.




This thesis is only available for download to the SIUC community. Current SIUC affiliates may also access this paper off campus by searching Dissertations & Theses @ Southern Illinois University Carbondale from ProQuest. Others should contact the interlibrary loan department of your local library or contact ProQuest's Dissertation Express service.