Date of Award
Master of Science
Electrical and Computer Engineering
Proposed is a formulation for quick diagnosis of the sources of failure in a failing system level test when functional input sequences are applied. We use implicit function based methods to identify the set of all possible input test sequences corresponding to a given output sequence. Our approach does quick defect isolation due to reduced complexity at the RT level abstraction of the circuit. The proposed formulation is modeled using Satisfiability Modulo Theories (SMT). Solvers based on SMT can effectively model RT level circuit descriptions written in behavioral and structural Verilog and much more efficient than traditional Boolean satisfiability. We are able to generate test pattern for all ISCAS’89 RTL benchmark and synthetic (ISCAS’89 RTL module connected to each other) circuits. Our result demonstrates quick defect detection and diagnostic test generation.
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