Date of Award


Degree Name

Master of Science


Electrical and Computer Engineering

First Advisor

Wang, Haibo


This thesis investigates efficient circuit techniques to synthesize sinusoidal signals with extremely wide programmable frequency range, from DC to the Niquist Frequency with a 100MHz system clock. In practice it is often preferred to limit the output frequencies to one third of the clock frequency. The developed techniques target sensor self-testing and impedance sensing applications. Different from most existing direct digital synthesis works, which primarily target communication applications, requiring narrow frequency range but demanding small phase jitters, this work focuses on circuit techniques to achieve large programmable frequency range, high signal to noise ratio (SNR), and efficient circuit implementation. First, it develops a theoretical framework to estimate the SNR of the synthesized signals in terms of the key design parameters, including the number of fractional Bits in the phase accumulator, the address width of the lookup- table (phase jitter), the resolution of the samples stored in the lookup- table (amplitude quantization) and the reconstruction filter cut- off frequency and order. The accuracy of the developed framework is verified by both system-level simulations and hardware measurement results. Second, a novel circuit structure including internal programmable clock division function is developed in order to achieve large frequency range and to minimize circuit size and implementation cost. The work establishes a procedure to derive the optimal allocation of circuit resources to generate the input word to the phase accumulator and the accumulator itself for a given frequency accuracy requirement. The proposed design is implemented on a hardware platform, consisting of a Xilinx Spartan-6 FPGA device, a 12-bit DAC and a fourth-order RC reconstruction filter, and its performance is verified by measurement results. It also shows the proposed design only takes on 1.1%, 0.26% and 45% of the FPGA LUT, DFF and RAM resources, respectively.




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