Date of Award
Doctor of Philosophy
Electrical and Computer Engineering
Rapidly shrinking technology node and aggressive scaling of voltage have increased the probability of soft errors. In the current deep sub-micron technology, a small inaccuracy in computing the probability of occurrence of a soft error results in an unacceptably large chip failure rate. We propose a method that considers timing information to determine accurately the probability of SET propagation resulting into an error. Disjoint covers of appropriately formulated functions are used for the probability computations in order to consider re-convergent paths in the circuit. The probabilities are calculated at the output gate at different time instants that SET can propagate within a latching window considering electrical attenuation. Bayes' theorem is used to model the SET injection. The method is extended to consider multiple SETs. A novel method is proposed to enhance SET propagation probability and is shown how it can assist the hardening process. A method to determine a set of patterns is also proposed that must be applied at the inputs to determine propagation characteristics of the SET that are meaningful for hardening purposes. A heuristic based on the probabilistic framework for SET propagation is proposed to diagnose (on-line or off-line) the location and time of strike based on errors observed at multiple points. The proposed diagnostic framework requires a new approach to calculate the probability for SET propagation to multiple non-independent variables. It is shown experimentally that the error appearances at multiple observable points help in SET diagnosis. The time performance of the proposed diagnostic framework is compared against an alternative implementation. This is particularly important in on-line diagnosis. The proposed methods are experimentally verified on ISCAS and ITC benchmarks considering both fixed gate delays and probability distribution function gate delays .
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