Date of Award
Doctor of Philosophy
Electrical and Computer Engineering
In recent years due to extensive device scaling, delay testing has become an issue of great concern. Delay diagnosis approaches have been proposed to measure delays of complete paths at observable points to provide an indication of the defective gates. Measurable segment delays would have resulted in more accurate diagnostic resolution but no such method exists to our knowledge. In this work, efficient methodologies to measure the delay of embedded segments based on monitoring the IDDT current are presented. First, a method that uses built-in IDDT current sensors to measure the delay of segments is presented. Sensor insertion is assisted by Automatic Test Pattern Generation. Experimental evaluation in 45nm technology shows that the approach measures segment delays in the presence of process variations, and under corner cases in gate loads and strengths. Experimentation on the ISCAS85, ISCAS89 and ITC99 benchmarks shows effectiveness of the approach in measuring the delay of all segments from some primary input to each gate with very low hardware overhead. Then, an ATPG methodology that measures the delays of embedded segments by IDDT current measurement for a circuit. The ATPG method utilizes two pairs of patterns so that the delay of an embedded segment that contains a small number of gates is measured with high accuracy. The method is capable of detecting a small cumulative defect along the embedded segment. Experimental results on some of the largest ISCAS85, ISCAS89 and ITC99 benchmarks show that the proposed ATPG tool generates pairs of patterns which measure the delay of many embedded segments.
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