Date of Award
Doctor of Philosophy
Electrical and Computer Engineering
The limited benefits of strain engineering in extremely scaled silicon devices and a lack of demonstrated gain in performance at the product level in nanowires, nanotubes, graphene, and other exotic channel materials give good reason to continue semiconductor device scaling using high-transport III-V (such as InGaAs and InAsSb) channel materials beyond the year 2020. Novel process techniques, such as ALD, layer transfer, high-k dielectrics, and metal gates are now being used to explore these MOSFETs. III-V materials are also being investigated for possible use in quantum-mechanical devices (such as tunnel transistors), in spin-FET devices, and in qubits and memory cells. However, there are several challenges (such as, low ION/IOFF ratio) associated with III-V MOSFETs that prohibit their use in high- performance and low-power logic applications. To address some of these challenges, in this work, we investigate the performance of tri-gate III-V FETs (with 18nm and 9nm channel lengths) as compared to the single-gate counterparts, and show how quantum size-quantization and random dopant fluctuations (RDF) affect the tri-gate FET characteristics and how to curb these issues. For this purpose, a 3-D fully atomistic quantum-corrected Monte Carlo device simulator has been integrated and used in this work. The size-quantiza¬tion effects have been accounted for via a param¬eter-free effec¬tive potential scheme and benchmarked against the NEGF approach in the ballistic limit. To study the RDF effects and treat full Coulomb (electron-ion and electron-electron) interactions in the real-space and beyond the Poisson picture, the simulator implements a corrected Coulomb electron dynamics (QC-ED) approach. The essential bandstructure and scattering parameters (bandgap, effective masses, and the density-of-states) have been computed using a 20-band nearest-neighbour sp3d5s* tight-binding scheme. Among various III-V materials studied in this work (such as GaAs, GaSb, InAs, InSb, and InAsSb), InAs0.7Sb0.3, when used with appropriately engineered gate metal workfunction, was found to deliver the largest ION/IOFF ratio. As for the gate oxide, per the recipe of several experimental groups, to overcome the direct tunnel leakage current that accrues with using oxide thicknesses less than 2nm, SiO2 has been replaced with HfO2. From the simulation results, ION with HfO2 was found to be approximately two times higher than that with SiO2. For 18-nm channel length, the trigate architecture, as compared to the single-gate counterpart, offered better sub-threshold swing, higher (~2×) ON current, and reduced off-current at VDS = 0.5V. Of the various scattering mechanisms considered in the simulations, surface roughness was found to be most critical, which degraded the drive current by almost 34% and 22% in the single-gate and trigate devices, respectively. However, the effect of surface roughness diminishes drastically as the channel length is scaled down to 9 nm. On the flip side, small effective masses as observed in these material systems, although preferred for high mobility and injection velocity, results in a significant reduction in inversion layer charge. Additionally, small effective mass, especially in reduced dimensionality (nanowire) structures, leads to strong quantum mechanical effects and further degradation in the drive current. With regard to the intrinsic parameter fluctuation, it was found that, although both the planer and the tri-gate transistors experience some fluc¬tuation in threshold voltage due to randomness in the chan¬nel region, this deviation is smaller in the trigate architecture. Finally, the random dopant fluctuation (RDF) effect was found to be weaker in a 9-nm channel device than the 18-nm counterpart.
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