Date of Award
Master of Science
Electrical and Computer Engineering
In this work, we propose an approach to detect and capture undesirable and unexpected process parameter variations in a circuit post-fabrication. We rely on delay measurable paths to detect deviations in path delays post-fabrication. We propose an algorithm to isolate suspect gates along failed paths using fault free delay measurable paths. Compact data structures like ZBDDs are used to store and manipulate paths. Experimental analysis using the proposed algorithm provides statistics of isolated gates along paths in various benchmark circuits. Further, we propose an algorithmic model that analyzes the suspect gates based on their topology along a path and reports the process parameter deviation for each such suspect gate.
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