An automatic test pattern generation approach to
detect delay defects in a circuit consisting of current mode
threshold logic gates is introduced. Each generated pattern
should excite the maximum propagation delay at the fault site.
Manufactured weights may vary, and maximum delay is ensured
by applying an appropriately generated set of patterns per fault.
Experimental results show the efficiency of the proposed methods.
Palaniswamy, Ashok Kumar, Tragoudas, Spyros and Haniotakis, Themistoklis. "ATPG for Delay Defects in Current Mode Threshold Logic Circuits." IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS PP, No. 99 (Jan 2016). doi:10.1109/TCAD.2016.2533863.