Date of Award
Doctor of Philosophy
Electrical and Computer Engineering
Current methodologies for built-in test pattern generation usually employ a predetermined linear feedback shift register (LFSR) in order to generate or decompress deterministic test patterns. As a direct consequence, the test pattern computation and the fault coverage are constrained to the preselected architecture. Work has been done to determine desirable characteristics in the LFSR to be used. Also, work has been done in the use of these predefined architectures, in order to compact the test data. In general, these methodologies take advantage of the large amount of don't care bits present in the test patterns, to accommodate the few specified bits to the output generated by the predefined LFSR. This dissertation explores the design of the LFSR as a built-in mechanism for test pattern generation in integrated circuits. The advantage of designing such devices is that the test set generation process is not constrained to a predefined LFSR mechanism, and the fault coverage is not affected. The methodologies presented in this work are based on cryptography concepts and heuristics to perform its computation. First, it is shown how these concepts can be adapted to test pattern generation. After this, methodologies are presented to generate one-dimensional and two-dimensional test sets. For the case of two-dimensional test set, the design of phase shifters is included.
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