Date of Award
8-1-2026
Degree Name
Doctor of Philosophy
Department
Electrical and Computer Engineering
First Advisor
Wang, Haibo
Abstract
The rapid proliferation of the Internet of Things (IoT) has introduced significant security challenges, particularly concerning stealthy, instruction-level malicious code injections that evade traditional software defenses. While conventional power analysis techniques are highly effective at detecting such subtle abnormalities, they require capturing high-resolution, voluminous power trace data. This dependency necessitates bulky data acquisition (DAQ) instrumentation, power-hungry analog-to-digital converters (ADCs), and intensive computational resources, making these methods impractical for deployment on resource-constrained IoT devices. To bridge this critical gap, this dissertation presents a novel hardware security paradigm, the Power Rising and Descending Signature (PRIDES) methodology. Instead of quantizing actual power consumption values, the proposed method generates a highly compact binary bitstream that characterizes the rising and falling trends of a device’s dynamic power consumption. By capturing only the fluctuation patterns, the PRIDES methodology drastically reduces data complexity, transmission overhead, and memory footprints. The proposed methodology introduces low-overhead, highly sensitive, and robust PRIDES generation circuits, validated in both 90 nm and 45 nm CMOS technologies, that achieve very high amplification gains without requiring dedicated pre-amplification stages. This circuit consumes only microwatts of power and occupies an ultra-compact active area, resulting in significantly less overhead compared to conventional ADCs in similar nodes by orders of magnitude. For signature analysis, a computation-light binary cross-correlation framework is developed for on-device abnormality detection, supported by a novel heuristic algorithm for generating optimal golden signatures. Notably, compared with conventional Pearson Correlation Coefficient (PCC)- based anomaly detection, which relies on floating-point arithmetic, the proposed bit-wise PRIDES analysis achieves comparable detection margins while executing orders of magnitude faster on computationally constrained microcontroller units (MCUs). To further minimize hardware overhead, an innovative topology is presented that seamlessly embeds the PRIDES generation mechanism directly into analog Low-Dropout (LDO) voltage regulators, providing dual-purpose power management and operational security. Crucially, circuit simulations demonstrate that this LDO-integrated design is highly resilient to typical off-chip component tolerances, affirming its practical validity by maintaining robust detection capabilities even with large variations in frequency-compensation capacitance. Furthermore, a comprehensive machine learning (ML)-based remote attestation framework is proposed. Extensive experimental evaluations using MCUs running standard benchmark routines demonstrate that the PRIDES methodology achieves detection accuracy comparable to raw power trace analysis while maintaining a significantly lower false-positive rate (FPR). Within this ML framework, experiments reveal that the PRIDES sampling rate can be aggressively down-sampled relative to the monitored device’s clock frequency without degrading classification accuracy, thereby further minimizing the signature size and data payload. By encoding only directional trends rather than actual power consumption values, PRIDES exhibits superior robustness against severe environmental stressors. It successfully maintains high detection fidelity across device-to-device Process variations, supply Voltage reductions, and Temperature variations (PVT), ultimately preserving the information necessary for reliable abnormality detection and operational integrity verification in resource-constrained IoT ecosystems.
Access
This dissertation is Open Access and may be downloaded by anyone.