Date of Award
Doctor of Philosophy
Electrical and Computer Engineering
In deep sub-micron, the decrease in feature size of the transistor has led to increasing challenge in testing an integrated circuit for delay defects. Small Delay Defects (SDD) have become predominant with aggressive scaling of the transistors. SDDs occur within gates, and interconnect. The traditional stuck-at, and transition fault model are not appropriate to model such defects. They must be tested appropriately by targeting critical paths in the circuit. Furthermore, reliability issues such as Negative Bias Temperature Instability (NBTI) and Hot carrier injection impact the threshold voltage of a transistor which, in turn, affect path delays. This necessitates selecting critical paths and formulating test methods that consider the above factors. An efficient method to select critical paths in the presence of small delay defects is presented. Due to the limitations in test application time, only a limited number of test patterns are applied that only sensitize a small subset of the critical paths. The paths are selected such that the defect probability density function of any node n in the circuit is maximized. The method uses the established linear parameterized model to encapsulate variations in process parameters. Experimental results on ISCAS ’85’, ’89’ and ITC ’99’ benchmarks demonstrate the scalability of the approach. In the presence of NBTI effects, the set of critical paths obtained at manufacturing time may change at a later time because paths age differently. An approach that generates a test set TL that target a set of paths PL (|TL|<|PL|) that become critical over the product life span L is presented. The critical paths in PL characterize timing behavior of the circuit considering process related variations. In addition, a pin-to-pin aging degradation model is introduced that accurately computes path delays. Experimental results on ISCAS ’85’,’89’ and ITC ’99’ benchmarks demonstrate the scalability of the approach. Finally, a BIST mechanism to detect counterfeit circuits which experience aging delays is presented. The approach is based on the NBTI aging factor. HSPICE simulations on 45nm and 65nm technologies using a predictive NBTI degradation model are presented. The results indicate that counterfeit circuits undergone minimal stress are detected consistently in the presence of process variations.
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