Date of Award
Master of Science
Electrical and Computer Engineering
In this paper, we highlight an effective approach that deals with the circuit delay post fabrication. This approach addresses certain issues in post silicon debug. Our approach takes into account the intra-die and inter-die variations and aims at determining the actual parameters associated with each cell on the fabricated VLSI chip. We present a methodology that determines the delay of each cell on the fabricated VLSI chip by performing empirical analysis on measurable paths in the circuit.
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