Published in Durbha, S.R., Laknaur, A., & Wang, H. (2006). Investigating the efficiency of integrator-based capacitor array testing techniques. Proceedings of the 24th IEEE VLSI Test Symposium (VTS’06). doi: 10.1109/VTS.2006.42 ©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.


This paper presents techniques to model the impact of parametric faults on the performance of programmable capacitor arrays (PCAs). Closed-form equations are derived for estimating ranges of parametric faults that can be detected by integrator-based PCA testing circuits. Methods to improve PCA testing efficiency are discussed and experimental results are reported.