ESD protection devices comprising polysilicon resistor, Vcc and Vss connected diodes with different sizes of PN junction area were fabricated on CMOS test chip and underwent ESD stress. The result of testing shows that larger PN junction area will subject the polysilicon resistor to bear more energy from ESD stress and end up with more failures. The relationship between stressing energy and junction area is hereby derived. Different failure modes for positive and negative ESD pulses are also identified. By comparing our own design with those of commercial designs, a safe length of contacting parameter at Al-polysilicon contact capable of handling the discharging current is identified to be more than 90 μm.