Published in Liu, P.C., Lee, B., Lian, E.A., Hock, G.C., & Wang, H. (1995). The related effects of increased PN junction area on ESD protection capability. Proceedings of the 1995 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 116-120. doi: 10.1109/IPFA.1995.487607 ©1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.


ESD protection devices comprising polysilicon resistor, Vcc and Vss connected diodes with different sizes of PN junction area were fabricated on CMOS test chip and underwent ESD stress. The result of testing shows that larger PN junction area will subject the polysilicon resistor to bear more energy from ESD stress and end up with more failures. The relationship between stressing energy and junction area is hereby derived. Different failure modes for positive and negative ESD pulses are also identified. By comparing our own design with those of commercial designs, a safe length of contacting parameter at Al-polysilicon contact capable of handling the discharging current is identified to be more than 90 μm.