It is attractive to design power efficient and robust SRAM in low voltage and high performance systems for mobile or battery-powered electronics. To reduce the power consumption resulting from bit-line activities, a new bit-line charge recycling circuit is proposed for 8T SRAMs. By eliminating the use of analog blocks required in existing circuits in literature, this proposed charge recycling scheme results in less design complexity. In addition, two types of SRAM cells are employed to improve the robustness in write operation, and hierarchical bit-line structure is applied to reduce the power consumption in read operation. Post-layout simulations demonstrate the proposed design results in 3.08 and 2.62 times enhancement of WSNM and SWN compared to conventional 6T SRAM design in the same technology, respectively. The power consumption of proposed design results in a reduction of 64.2% and 27.5% in write and read power consumption compared to 6T SRAM design. Moreover, given the same supply voltage (e.g., 1.2 V), post-layout simulation shows the proposed design is able to run at 5 times higher clock rate than the existing designs in literature. Given the same clock frequency requirement (e.g., 100 MHz), a lower supply voltage (e.g., 0.7 V) can sustain robust operation of the proposed design.