Date of Award
Master of Science
Electrical and Computer Engineering
Threshold logic gates have the capability of realizing complex Boolean functions with smaller number of logic gates . These gates are very sensitive to their weight values which may change during manufacturing process. So Threshold logic gates should be carefully designed to allow for maximum deviation from desired design weight values without affecting its functionality . This maximum allowable deviation is known as Fault Tolerance of the gate. ILP is one of the methods to find the optimum weight values with fault tolerance. But ILP has inability to solve the threshold functions with large inputs. This thesis presents two methods to overcome this difficulty.First one is the Combination method which combines the procedures of both decomposition method and ILP method .Second one is the Variable collapsing method which uses the principle of Variable Collapsing to find weights values with fault tolerance for large input functions.
This thesis is only available for download to the SIUC community. Others should
contact the interlibrary loan department of your local library.