Date of Award

12-1-2010

Degree Name

Master of Science

Department

Electrical and Computer Engineering

First Advisor

Ramaprasad, Harini

Abstract

There has been a lot of work that has been done on timing predictability of real-time tasks on embedded systems. The main assumption in these studies has been that the timing behavior has been based on single processor systems. The scenario has changed entirely when the single core systems have been replaced with the new Multicore systems. The timing predictability is controlled by the migrating tasks, the network topology connecting the cores and the number of cores on the system. In this thesis we come up with a feasibility analysis which depends on the characteristics of the tasks viz. number of cache lines, time of migration, available bandwith, number of tasks etc. We also test this analysis on novel mechanisms of migration which have been proposed recently and present its results.

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