Date of Award
Master of Science
Electrical and Computer Engineering
Network on Chip (NoC) architectures is an emerging paradigm for designing VLSI systems implemented on a single silicon chip. Recent activities focus on improvements in power consumption and in performance. This thesis focuses on real time aspects. It is shown that deadlines are met through preemptive scheduling. In particular, experimental studies show an average of 11% improvement in performance over existing non-preemptive methods. Keywords: High-level synthesis, scheduling, contention awareness, preemption, NoC.
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