Date of Award

12-1-2014

Degree Name

Master of Science

Department

Electrical and Computer Engineering

First Advisor

Sayeh, Mohammad

Abstract

The Discrete Cosine Transform (DCT) is one of the basic digital coding algorithms. Moreover, DCT is used in standard algorithms such as image (JPEG) and video (MPEG, H.26x) compression. Many researches are working to optimize DCT for its important implementation. Our focus in this thesis is on reducing the number of DCT operation throughout its calculation. In this thesis, we design hardware implementations of 4-point one-Dimensional DCT on Field Programmable Gate Arrays (FPGAs) technology using the Loeffler's algorithm, as multiplications required in Loeffler's algorithm are less than some other algorithms. Four and eight-point 1-D DCT coefficients have been calculated and then translated to matrix. By using Loeffler's algorithm method, 4 and 8-point DCT are translated to Loeffler's algorithm butterflies. The butterflies have number of stages that can be executed in series order. Only 4-point DCT and 4-point Loeffler's algorithm are designed here and their results are compared. The architecture of both algorithms is written in Verilog HDL code. Xilinx- ISE tool is used to synthesize the design. The code is downloaded into Spartan 3-E family XC3S500E FPGA board. Finally, all of the possible numbers that we could simulate and implement are tested with different means (manual, simulation, and implementation). The results of these means are compared and found identical. All forms of testing worked correctly for the selected inputs.

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