Published in Laknaur, A., & Wang, H. (2006). Design of window comparators for integrator-based capacitor array testing circuits. Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED’06). doi: 10.1109/ISQED.2006.47 ©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.


This paper investigates the impact of window comparator threshold variations on the performance of integrator-based programmable capacitor array (PCA) testing circuits. It presents two window comparator designs that take different approaches to address the problem of comparator threshold variations in PCA testing. The first comparator design utilizes a fully symmetric circuit structure to achieve small threshold deviations. The second design relies on increasing testing time to reduce the effect of comparator threshold variations. Experimental results are presented to compare the performance of the two design approaches.