Published in Raghuraman, K., Wang, H., & Tragoudas, S. (2006). Minimizing FPGA reconfiguration data at logic level. Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED’06), 224. doi: 10.1109/ISQED.2006.87 ©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.


A framework that relates the size of FPGA reconfiguration data to the number of minterms of a specially constructed function is presented. Three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. The method to integrate the proposed techniques into FPGA design automation flow is discussed and experimental results are presented.