Date of Award
Doctor of Philosophy
Electrical and Computer Engineering
A new data capturing technique for a potentially coupled bus of lines is proposed that always accommodates fast operation. The proposed method utilizes multiple reference voltages available within a line's receiving logic and the initial conditions of the involved wires in order to determine early and accurately the transmitted data in the current cycle. The presented data reading technique rarely requires repeater insertion and it can considerably accelerate signal propagation. The introduced logic at the receiver-end of a victim wire entails an affordable area overhead. Experimental results are given in the 65nm CMOS process for interconnects of various lengths. An architecture is proposed that allows for data reading with fault detection capability on lines which are likely to operate under a potentially wide range of capacitive coupling. In order to develop such a methodology, multiple reference or threshold voltages in the receiving logic of the lines are considered instead of typically one. The proposed technique utilizes the additional reference voltages to evaluate whether an intermittent fault has occurred during the capture of the transmitted data. Some combinational logic is introduced on the receiver side to accomplish this task. The mechanism is initially illustrated on a line with one adjacent aggressor. Subsequently, the case of a line with two adjacent aggressors is discussed and it is shown how to generalize the technique for wide buses. In this work the efficiency of the detection mechanism is evaluated for both single and multiple faulty occurrences. A novel circuit to treat crosstalk induced glitches on local interconnects is presented. Design irregularities and manufacturing defects on wires may result in spurious electrical events that impact the reliability of the interconnect infrastructure. The proposed methods act by dynamically adjusting the threshold voltage of the receiving gate on the victim line. The proposed technique can be used in combination with encoding algorithms on data buses. A comparative study in the 180nm CMOS process is presented that supports the applicability of the approach. Transient faults due to radiation have become increasingly observable in combinational logic. This is due to the weakening of inherent protective mechanisms that logic traditionally held against such flawed spurious events. Further boosting of such effects is increasingly probable due to the interaction of transients appearing at the inputs of logic gates. Such multiple instances of transients can arise either because of re-convergent circuit paths or because of significant reduction in the critical charge of modern technologies. The latter, in particular, makes more than one circuit nodes susceptible to the same high energy ions. A static transient propagation is employed to address possible transient interaction and to compute its worst-case effects in logic. The quantified effects of interest are the maximum duration and slope of the resulting hazards at the circuit outputs. A hardening methodology is also proposed to protect combinational logic from such events. For this purpose, filtering circuits are inserted in logic and several placement algorithms are developed and evaluated.
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